Some embodiments relate to a memory device comprising a charge-trapping layer disposed between a control gate and a select gate. The latch member includes a pair of bent portions configured for attaching to the data storage device, and an operating portion connecting with the bent portions. The FPDL provides syntactical elements for specifying the allocation of forwarding path structures as well as enabling the run-time construction of internal forwarding paths to interconnect the forwarding path structures in a manner specific to packet, packet flow, andor interface properties, for example. The encapsulant is formed over and covers the one or more electronic devices.