A shift register circuit comprises a plurality of stages, each stage being for providing an output signal to an output load and comprising a pull up transistor for pulling the output signal up to a high voltage rail and a pull down transistor for pulling the output signal down to a low voltage rail. The set is covered from the top and side of the bench by carpet decorative layer. A size of data buffered in the ingress buffer is compared to a frame ingress size for data to be buffered in the ingress buffer for a frame to be transmitted to the host. An o-ring gland disposed on the end of the housing may form a dynamic seal with the distraction rod. Conductors to be welded are inserted into the weld chamber through the guide sleeves. A locking device is formed by at least one casing, which houses therein at least one elastic element.