A system, probe interface, and method to test an integrated circuit with an electrostatic discharge signal. The tie-down includes a plate with a recess formed therein, and at least two arms traversing the recess. The method comprises the following steps: checking a cell-specific first SRS transmission subframe set; checking a relay-specific second SRS transmission subframe set; and allocating a resource for the uplink signal transmission. If so, the memory controller compares the data stored in the error correction chip with the data of the auxiliary memory. Various methods of the present invention allow creation of semiconducting andor conducting devices from readily grown SWNT carpets rather than requiring the preparation of a patterned growth channel and takes advantage of the self-controlling nature of these carpet heights to ensure a known and controlled channel length for reliable electronic properties as compared to the prior methods.