A motor speed control circuit generates a half cycle waveform and applies the half-cycle waveform to the motor at a controlled frequency to achieve speed reduction in the motor without motor modification. A plurality of Fibre Channel devices, such as workstations, are connected to a Fibre Channel transport medium, and a plurality of SCSI storage devices are connected to a SCSI bus transport medium The storage router interfaces between the Fibre Channel transport medium and the SCSI bus transport medium. Data can then be written to, or read from, the enabled memory cells in a single memory-access cycle.