According to an embodiment, a nonvolatile semiconductor memory device comprises: a semiconductor layer; a first gate insulating film; a plurality of floating gate electrodes; a second gate insulating film; a plurality of control gate electrodes; and an upper insulating film. The widths andor voltage levels of programming pulses are set to achieve programming of all memory cells of an array using a minimum number of programming pulses. The two sections may be connected by a weld, a suture, a common graft, an overlapping portion of the two sections, or one or more filaments of one section looping through portions of the other section. A restraining body is removably connected to the elongated lead body releasably exerting a force substantially counter to the biases of the first biased portion and the second biased portion. A pivot bracket or a second recliner mechanism is coupled to the first end of the lower cross bracket member for a dual-sided recliner system. The output signal is processed based at least in part upon the first and second intensity levels to form at least one image portion of the indicia.