Disclosed is a method of manufacturing a mechanically and chemically embossed surface covering having selectively textured surfaces. A trench isolation surrounds the planar NFET device and the planar PFET device penetrating through the SOI and abutting the insulator. The first and second wheel pieces may include respective first and second rim portions. Each of the plurality of bit line node contacts connects a corresponding bit line to the substrate, and each of the plurality of bit line node contacts has a width substantially equal to a width of the corresponding bit line. The latching hook and the pin engage with the sleeve when the button is in its activated position to secure the locking of the attachment with the end of the pin engaged in a receptacle formed on the surface of the sleeve to prevent rotation of the bayonet ring.