Provided are display panel, method of manufacturing the same, and frit composition used in the display panel. A first or driver stage biased in a near-A region with low distortion is cascaded with a second or power stage biased in a near-C region with high efficiency. After that, by using each sidewall insulating film as a mask, metal silicide layers are selectively formed on each surface of the semiconductor substrate and the gate electrode. A selector mechanism operates to select one of the N inputs for connection to a load for test purposes.