A route bypassing a root node is constructed in a network in which a spanning tree is formed. The body has a chamber and two through holes communicating with the chamber. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems. A dielectric layer is formed over the substrate and has a depth configured to form a well over the gate conductor. The lid 1 also includes a projection 18 extending from a portion of the side wall 6.