A switch mode power supply in which a control loop responsive to an input signal representative of the power supply output to provide a compensated error signal; and a PWM signal generator responsive to the compensated error signal to generate a variable duty cycle drive signal for the drive circuit having a selectable repetition rate. The output speed is calculated during a period of a shifting operation in which the current gear is disengaged and the new gear has yet to be engaged. Furthermore, the gaming device enables the player to pick one of the groups in the sequence. In some cases control may come from the associated PLD core circuitry. Reading of the cards is effected after cards have been received into a card holding area and before cards have been delivered into a card collection area from which cards are removed from the device for use. The gate electrode, the gate insulating film and the oxide semiconductor layer overlap in a plan view.